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this is information on a product in full production. february 2013 doc id 13356 rev 8 1/32 32 lnbh23 lnbs supply and control ic with step-up and i2c interface datasheet ? production data features complete interface between lnb and i2c bus built-in dc-dc converter for single 12 v supply operation and high efficiency (typ. 93% @ 0.75 a), with integrated nmos selectable output current limit by external resistor compliant with main satellite receiver systems specifications new accurate built-in 22 khz tone generator suits widely accepted standards (patent pending) fast oscillator start-up facilitates diseqc? encoding built-in 22 khz tone detector supports bi- directional diseqc? 2.0 very low-drop post regulator and high efficiency step-up pwm with integrated power nmos allow low power losses two output pins suitable to by-pass the output r-l filter and avoid any tone distortion (r-l filter as per diseqc? 2.0 specs, see typ. application circuits) overload and over-temperature internal protections with i2c diagnostic bits output voltage and output current level diagnostic feedback by i2c bits lnb short circuit dynamic protection 4 kv esd tolerant on output power pins description intended for analog and digital satellite receivers/sat-tv, sat-pc cards, the lnbh23 is a monolithic voltage regulator and interface ic, assembled in powersso-24 epad and qfn32 (5 x 5 mm.) epad, specifically designed to provide the 13/18 v power supply and the 22 khz tone signalling to the lnb down-converter in the antenna dish or to the multi-switch box. in this application field, it offers a complete solution with extremely low component count, low power dissipation together with simple design and i2c standard interfacing. qfn32 (5 x 5 mm.) (exposed pad) powersso-24 (exposed pad) table 1. device summary order code package packaging lnbh23ppr powersso-24 (exposed pad) tape and reel LNBH23QTR qfn32 (exposed pad) tape and reel www.st.com
contents lnbh23 2/32 doc id 13356 rev 8 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 diseqc? data encoding and decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 diseqc? 2.0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 diseqc? 1.x implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4 data encoding by external tone generator (extm) . . . . . . . . . . . . . . . . . . 5 2.5 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.7 diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.8 output voltage diagnostic - vmon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.9 22 khz tone diagnostic - tmon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.10 minimum output current diagnostic - imon . . . . . . . . . . . . . . . . . . . . . . . . 6 2.11 output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.12 over-current and short circuit protection and diagnostic . . . . . . . . . . . . . . 7 2.13 thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 i2c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.3 byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.5 transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 lnbh23 software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1 interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.2 system register (sr, 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
lnbh23 contents doc id 13356 rev 8 3/32 7.3 transmitted data (i2c bus write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.4 diagnostic received data (i2c read mode) . . . . . . . . . . . . . . . . . . . . . . . . 17 7.5 power-on i2c interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.6 address pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.7 diseqc? implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9 typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
block diagram lnbh23 4/32 doc id 13356 rev 8 1 block diagram figure 1. block diagram sda scl lnbh23 addr a-gnd i2c diagnostics i2c interface dsqin vup vorx votx lx 22khz oscill. pwm controller rsense en vsel linear post-reg +modulator +protections +diagnostics itest ttx en vsel vout control extm p-gnd preregulator +u.v.lockout +p.on reset byp vcc vcc- l isel ttx ten dsqout detin 22khz tone amp. diagn. 22khz tone freq. detector ttx vctrl sda scl lnbh23 addr a-gnd i2c diagnostics i2c interface dsqin vup vorx votx lx 22khz oscill. 22khz oscill. pwm controller rsense en vsel linear post-reg +modulator +protections +diagnostics itest ttx en vsel vout control extm p-gnd preregulator +u.v.lockout +p.on reset byp vcc vcc- l byp vcc vcc- l isel ttx ten dsqout detin 22khz tone amp. diagn. 22khz tone freq. detector ttx ttx vctrl
lnbh23 application information doc id 13356 rev 8 5/32 2 application information this ic has a built-in dc-dc step-up converter with integrated nmos that, from a single source from 8 v to 15 v, generates the voltages (v up ) that let the linear post-regulator to work at a minimum dissipated power of 0.375 w typ. @ 500 ma load (the linear post- regulator drop voltage is internally kept at v up -v orx =0.75 v typ.). an under voltage lockout circuit will disable the whole circuit when the supplied v cc drops below a fixed threshold (6.7 v typically). note: in this document the output voltage (v o ) is intended as the voltage present at the linear post-regulator output (v orx pin). 2.1 diseqc? data encoding and decoding the new internal 22 khz tone generator (patent pending) is factory trimmed in accordance to the standards, and can be selected by i2c interface ttx bit (or ttx pin) and activated by a dedicated pin (dsqin) that allows immediate diseqc? data encoding, or through ten i2c bit in case the 22 khz presence is requested in continuous mode. in stand-by condition (en bit low) the ttx function must be disabled setting ttx to low. 2.2 diseqc? 2.0 implementation the built-in 22 khz tone detector completes the fully bi-directional diseqc? 2.0 interfacing (see note 1 ). it?s input pin (detin) must be ac coupled to the diseqc? bus, and extracted pwk data are available on the dsqout pin. to comply to the bi-directional diseqc? 2.0 bus hardware requirements an output r-l filter is needed. the lnbh23 is provided with two output pins, one for the dc voltage output (v orx ) and one for the 22 khz tone transmission (v otx ). the v otx must be activated only during the tone transmission while the v orx provides the 13/18 v output voltage. this allows the 22 khz tone to pass without any losses due to the r-l filter impedance (see figure 4 typ. application circuit). during the 22 khz transmission, in diseqc? 2.0 applications, activated by dsqin pin or by the ten bit, the v otx pin must be preventively set on by the ttx function. this can be controlled both through the ttx pin and by i2c bit. as soon as the tone transmission is expired, the v otx must be disabled by setting the ttx to low to set the device in the 22 khz receiving mode. the 13/18 v power supply is always provided to the lnb from the v orx pin through the r-l filter. 2.3 diseqc? 1.x implementation when the lnbh23 is used in diseqc? 1.x applications the r-l filter is always needed for the proper operation of the new 22 khz tone generator (patent pending. see application circuit). also in this case, the ttx function must be preventively enabled before to start the 22 khz data transmission and disabled as soon as the data transmission has been expired. the tone can be activated both with the dsqin pin or the ten i2c bit. the dsqin internal circuit activates the 22 khz tone on the v otx output with 0.5 cycles 25 s delay from the ttl signal presence on the dsqin pin, and it stops with 1 cycles 25 s delay after the ttl signal is expired.
application information lnbh23 6/32 doc id 13356 rev 8 2.4 data encoding by external tone generator (extm) in order to improve design flexibility an external tone input pin is available (extm). the extm is a logic input pin which activates the 22 khz tone output, on the v otx pin, by using the lnbh23 integrated tone generator (similarly to the dsqin pin function). as a matter of fact, the output tone waveform characteristics will be always internally controlled by the lnbh23 tone generator and the extm signal will be used just as a timing control of the diseqc tone data encoding on the v otx output. a ttl compatible 22 khz signal is required for the proper control of the extm pin function. before to send the ttl signal on the extm pin, the v otx tone generator must be previously enabled through the ttx function (ttx pin or ttx bit set high). as soon as the extm internal circuit detects the 22 khz ttl signal code, it activates the 22 khz tone on the v otx output with 1.5 cycles 25 s delay from the ttl signal presence on the extm pin, and it stops with 2 cycles 25 s delay after the ttl signal is expired. refer to the below figure 2 . figure 2. extm waveform 2.5 i2c interface the main functions of the ic are controlled via i2c bus by writing 8 bits on the system register (sr 8 bits in write mode). on the same register there are 8 bits that can be read back (sr 8 bits in read mode) to provide 8 diagnostic functions: five bits will report the diagnostic status of five internal monitoring functions (imon, vmon, tmon, otf, olf) while, three will report the last output voltage register status (en, vsel, llc) received by the ic (see below diagnostic functions section). 2.6 output voltage selection when the ic sections are in stand-by mode (en bit low), the power blocks are disabled. when the regulator blocks are active (en bit high), the output can be logic controlled to be 13 or 18 v by means of the v sel bit (voltage select) for remote controlling of non-diseqc lnbs. additionally, the lnbh23 is provided with the llc i2c bit that increases the selected voltage value by +1 v to compensate the excess of voltage drop along the coaxial cable. the lnbh23 is also compliant to the usa lnb power supply standards. in order to allow fast transition of the output voltage from 18 v to 13 v and vice versa, the lnbh23 is provided with the vctrl ttl pin which keeps the output to 13 v when it is set low and to 18 v when it is set high or floating. v sel and, if required, llc bits must be set high before to use the vctrl pin to switch the output voltage level. if vctrl=1 or floating v orx =18.5 v (or 19.5 v if llc=1). with vctrl=0 v orx =13.4 v (llc= either 0 or 1). be aware that the vctrl pin controls only the linear regulator v orx stage while the step-up v up voltage is controlled only through the vsel and llc i2c bits, that is: even if vctrl=0 (keeping v orx =13.4 v) you will have v up =19.25 v typ when v sel =1 and 20.25 v with v sel =llc=1.
lnbh23 application information doc id 13356 rev 8 7/32 this means that vctrl=0 must be used only for short time to avoid the higher power dissipation. in stand-by condition (en bit low) all the i2c bits and the ttx pin must be set low (if the ttx pin is not used it can be left floating but the ttx bit must be set low during the stand-by condition). 2.7 diagnostic and protection functions the lnbh23 has 5 diagnostic internal functions provided via i2c bus by reading 5 bits on the system register (sr bits in read mode). all the diagnostic bits are, in normal operation (no failure detected), set to low. two diagnostic bits are dedicated to the over-temperature and over-load protections status (otf and olf) while, the remaining 3 bits, are dedicated to the output voltage level (vmon), 22 khz tone (tmon) and to the minimum load current diagnostic function (imon). 2.8 output voltage diagnostic - vmon when v sel =0 or 1 and llc=0, the output voltage pin (v orx ) is internally monitored and, as long as the output voltage level is below the guaranteed limits the vmon i2c bit is set to "1". the output voltage diagnostic is valid only with llc=0. any vmon information with llc=1 must be disregarded by the mcu. 2.9 22 khz tone diagnostic - tmon the 22 khz tone can be internally detected and monitored if detin pin is connected to the lnb output bus (see typical application circuits figure 4 ) through a decoupling capacitor. the tone diagnostic function is provided with the tmon i2c bit. if the 22 khz tone amplitude and/or the tone frequency is out of the guaranteed limits (see tmon limits in the electrical characteristics ta b l e 1 3 ), the tmon i2c bit is set to "1". 2.10 minimum output current diagnostic - imon in order to detect the output load absence (no lnb connected on the bus or cable not connected to the ird) the lnbh23 is provided with a minimum output current flag by the imon i2c bit in read mode, which is set to "1" if the output current is lower than 12 ma typically with itest=1 and 6 ma with itest=0. the minimum current diagnostic function (imon) is always active. in order to make it work even in a multi-ird configuration (multi- switch), where the supply current could be sunk only from the higher supply voltage connected to the multi-switch box, the lnbh23 is provided with the aux i2c bit which can be set high, in write mode by the mcu, before to read the imon i2c bit status, to force the lnbh23 output voltage as the highest voltage on the bus (22 v typ.) during the minimum current diagnostic phase. when the aux bit is set to high, the v orx is set to 22 v (typ.) and v up is set to 22.75 v (v up = v orx +0.75 v typ.) independently of the vsel/llc bits status. if the aux function is used to force the v orx to 22 v, it is recommended to set the aux bit to low as soon as the minimum current test phase is expired, so that the v orx voltage will be controlled again as per the vsel/llc bits status. in order to avoid false triggering, the imon function must be used only with the 22 khz tone transmission deactivated (ten=ttx=0 and dsqin=low), otherwise the imon bit could be erroneously set to 0 even if the output current is below the minimum current thresholds (6 ma or 12 ma). any tmon information with 22 khz tone enabled must be disregarded by the mcu.
application information lnbh23 8/32 doc id 13356 rev 8 2.11 output current limit selection the linear regulator current limit threshold can be set by an external resistor connected to i sel pin. the resistor value defines the output current limit by the equation: i max [a] = 10000/r sel where r sel is the resistor connected between i sel and gnd. the highest selectable current limit threshold is 1.0 a typ with r sel =10 k . the above equation defines the typical threshold value. 2.12 over-current and short circuit protection and diagnostic in order to reduce the total power dissipation during an overload or a short circuit condition, the device is provided with a dynamic short circuit protection. it is possible to set the short circuit current protection either statically (simple current clamp) or dynamically by the pcl bit of the i2c sr. when the pcl (pulsed current limiting) bit is set lo low, the over current protection circuit works dynamically: as soon as an overload is detected, the output current is provided for 90 ms (typ.), after that the output is set in shut-down for a time t off of typically 900 ms. simultaneously the diagnostic olf i2c bit of the system register is set to "1". after this time has elapsed, the output is resumed for a time t on =1/10 t off = 90 ms (typ.). at the end of t on , if the overload is still detected, the protection circuit will cycle again through t off and t on . at the end of a full t on in which no overload is detected, normal operation is resumed and the olf diagnostic bit is reset to low. typical t on +t off time is 990 ms and an internal timer determines it. this dynamic operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent power-on start-up in most conditions. however, there could be some cases in which a highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. this can be solved by initiating any power start-up in static mode (pcl=1) and, then, switching to the dynamic mode (pcl=0) after a chosen amount of time depending on the output capacitance. also in static mode, the diagnostic olf bit goes to "1" when the current clamp limit is reached and returns low when the overload condition is cleared. 2.13 thermal protection and diagnostic the lnbh23 is also protected against overheating: when the junction temperature exceeds 150 c (typ.), the step-up converter and the liner regulator are shut-off, and the diagnostic otf sr bit is set to "1". normal operation is resumed and the otf bit is reset to low when the junction is cooled down to 135 c (typ.). note: 1 external components are needed to comply to bidirectional diseqc? bus hardware requirements. full compliance of the whole application with diseqc? specifications is not implied by the use of this ic. notice: diseqc? is a trademark of eutelsat. i2c is trademark of philips semiconductors.
lnbh23 pin configuration doc id 13356 rev 8 9/32 3 pin configuration figure 3. pin connections (top view for powersso-24, bottom view for qfn32) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 nc isel vup nc votx vorx a-gnd vcc vcc-l byp detin nc vctrl nc lx p-gnd sda scl addr dsqout dsqin nc 14 13 ttx extm 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 nc isel vup nc votx vorx a-gnd vcc vcc-l byp detin nc vctrl nc lx p-gnd sda scl addr dsqout dsqin nc 14 13 ttx extm qfn32 (5 x 5 mm.) powersso-24 table 2. pin description pin n for qfn32 pin n for psso-24 symbol name function 19 17 v cc supply input 8 to 15 v ic dc-dc power supply. 18 16 v cc?l supply input 8 to 15 v analog power supply. 4 6 lx n-mos drain integrated n-channel power mosfet drain. 27 22 v up step-up voltage input of the linear post-regulator. the voltage on this pin is monitored by the internal step-up controller to keep a minimum dropout across the linear pass transistor. 21 19 v orx ldo output port output of the integrated low drop linear post-regulator. see truth tables for voltage selections and description. 22 20 v otx output port for 22 khz tone tx tx output to the lnb. see truth tables for selection. 6 8 sda serial data bi-directional data from/to i2c bus. 9 9 scl serial clock clock from i2c bus. 12 12 dsqin diseqc input this pin will accept the diseqc code from the main microcontroller. the lnbh23 will use this code to modulate the internally generated 22 khz carrier. set to ground if not used. 14 14 ttx ttx enable this pin can be used, as well as the ttx i2c bit of the system register, to control the ttx function enable before to start the 22 khz tone transmission. set floating or to gnd if not used. 29 1 detin tone decoder input 22 khz tone decoder input, must be ac coupled to the diseqc 2.0 bus.
pin configuration lnbh23 10/32 doc id 13356 rev 8 pin n for qfn32 pin n for psso-24 symbol name function 11 11 dsqout diseqc output open drain output of the tone decoder to the main microcontroller for diseqc 2.0 data decoding. it is low when tone is detected on detin pin. 13 13 extm external modulation external modulation logic input pin which activates the 22 khz tone output on the v otx pin. set to ground if not used. 15 15 byp by-pass capacitor needed for internal pre-regulator filtering. the byp pin is intended only to connect an external ceramic capacitor. any connection of this pin to external current or voltage sources may cause permanent damage to the device. 10 10 addr address setting two i2c bus addresses available by setting the address pin level voltage. see address pin characteristics ta bl e 1 0 28 23 isel current selection the resistor ?rsel? connected between isel and gnd defines the linear regulator current limit threshold by the equation: imax(typ.)=10000/ rsel. 30 2 vctrl output voltage control 13v-18v linear regulator v orx switch control. to be used only with v sel =1. if vctrl=1 or floating v orx =18.5v (or 19.5v if llc=1). if vctrl=0 than v orx =13.4v (llc=either 0 or 1). leave floating if not used. do not connect to ground if not used. 5 7 p-gnd power ground dc-dc converter power ground. epad epad epad exposed pad to be connected with power grounds and to the ground layer through vias to dissipate the heat. 20 18 a-gnd analog ground analog circuits ground. 1, 2, 3, 7, 8, 16, 17, 23, 24, 25, 26, 31, 32 3, 4, 5, 21, 24 n.c. not connected not internally connected pins. table 2. pin description (continued)
lnbh23 maximum ratings doc id 13356 rev 8 11/32 4 maximum ratings note: 1 absolute maximum ratings are those values beyond which damage to the device may occur. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. all voltage values are with respect to network ground terminal. 2 the byp pin is intended only to connect an external ceramic capacitor. any connection of this pin to external current or voltage sources may cause permanent damage to the device. table 3. absolute maximum ratings symbol parameter value unit v cc-l , v cc dc power supply input voltage pins -0.3 to 16 v v up dc input voltage -0.3 to 24 v i o output current internally limited ma v orx dc output pin voltage -0.3 to 25 v v otx tone output pin voltage -0.3 to 25 v v i logic input voltage (ttx, sda, scl, dsqin, extm, vctrl, addr) -0.3 to 7 v lx lx input voltage -0.3 to 24 v v detin detector input signal amplitude 2 v pp v oh logic high output voltage (dsqout) -0.3 to 7 v v byp internal reference pin voltage ( note 2 ) -0.3 to 4.6 v isel current selection pin voltage -0.3 to 4.6 v t stg storage temperature range -50 to 150 c t j operating junction temperature range -25 to 125 c esd esd rating with human body model (hbm) for all pins unless 6, 19, 20 (for psso24) and unless 4, 21, 22 (for qfn32) 2 kv esd rating with human body model (hbm) for pins 19, 20 (for psso24) and pins 21, 22 (for qfn32) 4 esd rating with human body model (hbm) for pin 6 (for psso24) and pin 4 (for qfn32) 0.6 table 4. thermal data symbol parameter qfn32 powersso-24 unit r thjc thermal resistance junction-case 2 2 c/w r thja thermal resistance junction-ambient (powersso- 24) with device soldered on 2s2p pc board 35 30 c/w
application circuit lnbh23 12/32 doc id 13356 rev 8 5 application circuit figure 4. typical application circuit l1=22h c11 220nf c6 470nf ceramic d3 1n4001 d3 1n4001 c3 100f c3 100f c5 100f l2 ferrite bead filter l2 suggested part number: murata bl01rn1-a62 panasonic excels a35 ferrite bead filter l2 suggested part number: murata bl01rn1-a62 panasonic excels a35 tone enable vin 12v 270h r4 15 ohm to lnb c12 10nf d2 bat43 d2 bat43 c13 10nf c13 10nf { i 2 c bus sda scl dsqin lx vup vcc- l vcc vorx detin votx byp extm dsqout addr c1 100f c8 220nf ceramic c8 220nf ceramic c7 100nf ceramic c7 100nf ceramic lnbh23 r2 (rsel) 11kohm isel ttx enable ttx p-gnd a-gnd c9 10f c9 10f vctrl r1 100ohm d4 bat43 d4 bat43 stps130a d1 stps130a d1 c4 470nf c4 470nf ceramic c10 220nf ceramic c10 220nf ceramic c2 100nf ceramic ceramic l3 13/18 r3 10kohm table 5. bill of material component notes r1, r4 1/4w resistors. refer to the typical application circuit for the relative values r2 (rsel), r3 1/4w resistors. refer to the typical application circuit for the relative values c1 25v electrolytic capacitor, 100f or higher is suitable. c9 10f, >35v electrolytic capacitor c3, c5 100f, >25v electrolytic capacitor, esr in the 150m to 350m range c2, c4, c6, c7, c8, c10, c11, c12, c13 >25v ceramic capacitors. refer to the typ. appl. circuit for the relative values d1 stps130a or any similar schottky diode with v rrm >25v and i f(av) higher than: i f(av) > i out_max x (v up_max /v in_min ) d2, d4 bat43, 1n5818, or any schottky diode with i f(av) > 0.2a, v rrm > 25 v, v f < 0.5 v d3 1n4001 or equivalent l1 22 h inductor with i sat >i peak where i peak is the boost converter peak current (see equation 1 )
lnbh23 application circuit doc id 13356 rev 8 13/32 to calculate the boost converter peak current (i peak ) of l1, use the following formula: equation 1 component notes l2 ferrite bead, panasonic-excels a35 or murata-bl01rn1-a62 or taiyo-yuden- bkp1608hs600 or equivalent with similar or higher impedance and current rating higher than 2a l3 220h-270h inductor with current rating higher than rated output current table 5. bill of material (continued)
i2c bus interface lnbh23 14/32 doc id 13356 rev 8 6 i2c bus interface data transmission from main mcu to the lnbh23 and vice versa takes place through the 2 wires i2c bus interface, consisting of the 2 lines sda and scl (pull-up resistors to positive supply voltage must be externally connected). 6.1 data validity as shown in figure 5 , the data on the sda line must be stable during the high semi-period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. 6.2 start and stop condition as shown in figure 6 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition of the sda line while scl is high. a stop condition must be sent before each start condition. 6.3 byte format every byte transferred to the sda line must contain 8 bits. each byte must be followed by an acknowledge bit. the msb is transferred first. 6.4 acknowledge the master (mcu) puts a resistive high level on the sda line during the acknowledge clock pulse (see figure 7 ). the peripheral (lnbh23) that acknowledges has to pull-down (low) the sda line during the acknowledge clock pulse, so that the sda line is stable low during this clock pulse. the peripheral which has been addressed has to generate acknowledge after the reception of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case the master transmitter can generate the stop information in order to abort the transfer. the lnbh23 won't generate acknowledge if the v cc supply is below the under voltage lockout threshold (6.7 v typ.). 6.5 transmission without acknowledge avoiding to detect the acknowledges of the lnbh23, the mcu can use a simpler transmission: simply it waits one clock cycle without checking the slave acknowledging, and sends the new data. this approach of course is less protected from misworking and decreases the noise immunity.
lnbh23 i2c bus interface doc id 13356 rev 8 15/32 figure 5. data validity on the i2c bus figure 6. timing diagram of i2c bus figure 7. acknowledge on the i2c bus
lnbh23 software description lnbh23 16/32 doc id 13356 rev 8 7 lnbh23 software description 7.1 interface protocol the interface protocol comprises: a start condition (s) a chip address byte (the lsb bit determines read(=1)/write(=0) transmission) a sequence of data (1 byte + acknowledge) a stop condition (p) ack = acknowledge s = start p = stop r/w = 1/0, read/write bit x = 0/1, two selectable addresses available through addr pin (see address pin characteristics ta b l e 1 0 ) 7.2 system register (sr, 1 byte) write = control bits functions in write mode read= diagnostic bits in read mode. all bits reset to 0 at power on 7.3 transmitted data (i2c bus write mode) when the r/w bit in the chip address is set to 0, the main mcu can write on the system register (sr) of the lnbh23 via i2c bus. all and 8 bits are available and can be written by the mcu to control the device functions as per the below truth table. chip address data msb lsb msb lsb s000101xr/wack ackp mode msb lsb write pcl ttx ten llc vsel en itest aux read imon vmon tmon llc vsel en otf olf
lnbh23 lnbh23 software description doc id 13356 rev 8 17/32 x = don't care all values are typical unless otherwise specified valid with ttx pin floating or to gnd 7.4 diagnostic received data (i2c read mode) lnbh23 can provide to the mcu master a copy of the diagnostic system register information via i2c bus in read mode. the read mode is master activated by sending the chip address with r/w bit set to 1. at the following master generated clocks bits, lnbh23 issues a byte on the sda data bus line (msb transmitted first). at the ninth clock bit the master can: acknowledge the reception, starting in this way the transmission of another byte from the lnbh23 no acknowledge, stopping the read mode communication three bits of the register are read back as a copy of the corresponding write output voltage register status (llc, vsel, en), while, the other five bits convey diagnostic information about the over-temperature (otf), output voltage level (vmon), output over-load (olf), minimum output current presence (imon) and 22 khz tone (tmon). in normal operation the diagnostic bits are set to zero, while, if a failure is occurring, the corresponding bit is set to one. at start-up all the bits are reset to zero. table 6. truth table pcl ttx ten llc vsel en itest aux function 00010v orx = 13.4v, v up =14.15v, (v up -v orx =0.75v) 00110v orx = 18.5v, v up =19.25v, (v up -v orx =0.75v) 01010v orx = 14.4v, v up =15.15v, (v up -v orx =0.75v) 01110v orx = 19.5v, v up =20.25v, (v up -v orx =0.75v) xx1x1v orx = 22v, v up =22.75v, (v up -v orx =0.75v) 0 1 22 khz controlled by dsqin pin (only if ttx=1) 1 1 1 22 khz tone output is always activated 01 v orx output is on, v otx tone generator output is off 11v orx output is on, v otx tone generator output is on 0 1 pulsed (dynamic) current limiting is selected 1 1 static current limiting is selected xx10 minimum output current diagnostic threshold = 6ma typ. xx11 minimum output current diagnostic threshold = 12ma typ. x x x x x 0 x x power block disabled
lnbh23 software description lnbh23 18/32 doc id 13356 rev 8 7.5 power-on i2c interface reset i2c interface built in lnbh23 is automatically reset at power-on. as long as the v cc stays below the under voltage lockout (uvl) threshold (6.7 v), the interface does not respond to any i2c command and the system register (sr) is initialized to all zeroes, thus keeping the power blocks disabled. once the v cc rises above 7.3 v typ. the i2c interface becomes operative and the sr can be configured by the main mcu. this is due to 500 mv of hysteresis provided in the uvl threshold to avoid false retriggering of the power-on reset circuit. 7.6 address pin it is possible to select two i2c interface addresses by means of addr pin. this pin is ttl compatible and can be set as per hereafter address pin characteristics ta b l e 1 0 . 7.7 diseqc? implementation lnbh23 helps system designer to implement bi-directional diseqc 2.0 protocol by allowing an easy pwk modulation/demodulation of the 22 khz carrier. between the lnbh23 and the main mcu the pwk data is exchanged using logic levels that are compatible with both 3.3 v and 5 v mcu. this data exchange is made through two dedicated pins, dsqin and dsqout, in order to maintain the timing relationships between the pwk data and the pwk modulation as accurate as possible. these two pins should be directly connected to two i/o pins of the mcu, thus leaving to the firmware the task of encoding and decoding the pwk data in accordance to the diseqc protocol. full compliance of the system to the specification is thus not implied by the bare use of the lnbh23. the system designer should also take in consideration the bus hardware requirements; that can be simply accomplished by the r-l termination connected between v orx and v otx pins of lnbh23, as shown in the typical application circuit in figure 4 . to avoid any losses due to the r-l impedance during the tone transmission, lnbh23 has dedicated tone output (v otx ) that is connected after the filter and must be enabled by setting the ttx function to high only during the tone transmission (see diseqc 2.0 operation implementation in section 2.2 and 2.3 ). also unidirectional diseqc 1.x and non- diseqc systems need this termination connected through a bypass capacitor and after a r- l filter with 15 in parallel with a 220 h-270 h inductor but, there is no need of tone decoding, thus detin and dsqout pins can be left connected to gnd. table 7. register imon vmon tmon llc vsel en otf olf function these bits are read exactly the same as they were left after last write operation 0t j < 135c, normal operation (1) 1t j > 150c, power blocks disabled (1) 0i o < i omax , normal operation 1i o > i omax , overload protection triggered 0/1 (2) 0/1 (3) 0/1 these bits are set to 1 if the relative parameter is out of the specification limits. 1. values are typical unless otherwise specified 2. imon information must be disregarded if 22 khz tone output is enabled 3. vmon information must be disregarded if llc=1 (valid only if llc=0)
lnbh23 electrical characteristics doc id 13356 rev 8 19/32 8 electrical characteristics refer to the typical application circuit, t j = 0 to 85 c, en=1, vsel=llc=ten=pcl=itest=ttx=aux=0, r sel = 11 k , dsqin = low, v i = 12 v, i o = 50 ma, unless otherwise stated. typical values are referred to t j = 25 c. v o = v orx pin voltage. see software description section for i2c access to the system register. table 8. electrical characteristics symbol parameter test conditions min. typ. max. unit v i supply voltage i o =750ma, vsel=llc=1 8 12 15 v i i supply current i o =0 7 15 ma en=ten=ttx=1, i o =0 20 40 en=0 2 v o output voltage aux=1; i o =50ma 22 v v sel =1 i o =750ma llc=0 17.8 18.5 19.2 llc=1 18.8 19.5 20.2 v sel =0 i o =750ma llc=0 12.8 13.4 14 llc=1 13.8 14.4 15 v o line regulation v i =8 to 15v vsel=0 5 40 mv vsel=1 5 60 v o load regulation v sel =0 or 1, i o from 50 to750ma 200 mv 13/18 t r - t f 13/18v rise and fall transition time by v ctrl pin v sel =llc=1, v ctrl from low to high and vice versa, i o from 6 to 450ma, c o from 10 to 330nf 575 s i max output current limiting r sel =11k 750 1000 ma r sel = 22k 300 600 i sc output short circuit current v sel =0/1, aux=0/1 1000 ma t off dynamic overload protection off time pcl=0, output shorted 900 ms t on dynamic overload protection on time pcl=0, output shorted t off /10 f tone tone frequency dsqin=high or ten=1, ttx=1 20 22 24 khz a tone tone amplitude dsqin=high or ten=1, ttx=1 i o from 0 to750ma c o from 0 to 750nf 0.4 0.650 0.9 v pp d tone tone duty cycle dsqin=high or ten=1, ttx=1 43 50 57 % t r , t f tone rise or fall time dsqin=high or ten=1, ttx=1 5 8 15 s f extm extm frequency v extm-h =3.3v, v extm-l =0v, (1) 20 22 24 khz eff dc-dc dc-dc converter efficiency i o =750ma 93 % f sw dc-dc converter switching freq. 220 khz f detin tone detector freq. capture range 0.4v pp sine wave (2) 19 22 25 khz
electrical characteristics lnbh23 20/32 doc id 13356 rev 8 t j from 0 to 85 c, v i = 12 v t j from 0 to 85 c, v i = 12 v symbol parameter test conditions min. typ. max. unit v detin tone detector input amplitude sine wave signal, 22 khz 0.3 1.5 v pp z detin tone detector input impedance 150 k v ol dsqout pin logic low detin tone present, i ol =2ma 0.3 0.5 v i oz dsqout pin leakage current detin tone absent, v oh =6v 10 a v il dsqin,ttx,13/18, extm pin logic low 0.8 v v ih dsqin,ttx,13/18, extm pin logic high 2v i ih dsqin,ttx,13/18, extm pin input current v ih =5v 15 a i obk output backward current en=0, v obk =21v -6 -15 ma t shdn thermal shut-down threshold 150 c t shdn thermal shut-down hysteresis 15 c 1. external signal frequency range in which the extm function is guaranteed. 2. frequency range in which the detin function is guaranteed. the v pp level is intended on the lnb bus (before the c12 capacitor. see figure 4 ) table 8. electrical characteristics (continued) table 9. i2c electrical characteristics symbol parameter test conditions min. typ. max. unit v il low level input voltage sda, scl 0.8 v v ih high level input voltage sda, scl 2 v i i input current sda, scl, v i = 0.4 to 4.5v -10 10 a v ol low level output voltage sda (open drain), i ol = 6ma 0.6 v f max maximum clock frequency scl 400 khz table 10. address pin characteristics symbol parameter test condition min. typ. max. unit v addr-1 "0001010(r/w)" address pin voltage range r/w bit determines the transmission mode: read (r/w=1) write (r/w=0) 00.8v v addr-2 "0001011(rw)" address pin voltage range r/w bit determines the transmission mode: read (r/w=1) write (r/w=0) 25v v addr-3 (1) "0001000(rw)" address pin voltage range r/w bit determines the transmission mode: read (r/w=1) write (r/w=0) 05v 1. this i2c address is reserved only for internal usage. do not use this address with other i2c peripherals to avoid address conflicts.
lnbh23 electrical characteristics doc id 13356 rev 8 21/32 refer to the typical application circuit, t j from 0 to 85 c, en=1, vsel=llc=ten=pcl=itest=ttx=aux=0, r sel =11 k , dsqin=low, v i = 12 v, i o = 50 ma, unless otherwise stated. typical values are referred to t j = 25 c. v o =v orx pin voltage. see software description section for i2c access to the system register. note: if the output voltage is lower than the min. value the vmon i2c bit is set to 1. when vsel=0: if vmon=0 then v orx >85% of v orx typical; if vmon=1 then v orx <95% of v orx typical. when vsel=1: if vmon=0 then v orx >84% of v orx typical; if vmon=1 then v orx <96% of v orx typical. t j from 0 to 85 c, en = 1, vsel=llc=ten=pcl=ttx=0, dsqin=low, v i = 12 v, unless otherwise stated. see software description section for i2c access to the system register. note: if the output current is lower than the min. threshold limit the imon i2c bit is set to 1. if the output current is higher than the max threshold limit the imon i2c bit is set to 0. refer to the typical application circuit, t j from 0 to 85 c, en = 1, vsel=llc=ten=pcl=itest=ttx=aux=0, r sel = 11 k , dsqin=low, v i = 12 v, i o = 50 ma, unless otherwise stated. typical values are referred to t j =25c. v orx =v orx pin voltage. see software description section for i2c access to the system register. note: if the 22 khz tone parameters are lower or higher than the above limits the tmon i2c bit is set to 1. table 11. output voltage diagnostic (vmon bit) characteristics symbol parameter test condition min. typ. max. unit v th-l diagnostic low threshold at v o =13.4v en=1, vsel=0 llc=0 85 90 95 % v th-l diagnostic low threshold at v o =18.5v en=vsel=1 llc=0 84 90 96 % table 12. minimum output current diagnostic (imon bit) characteristics symbol parameter test condition min. typ. max. unit i th minimum current diagnostic threshold itest=1, aux=0/1 5 12 20 ma itest=0, aux=0/1 2.5 6 10 table 13. 22 khz tone diagnostic (tmon bit) characteristics symbol parameter test condition min. typ. max. unit a th-l amplitude diagnostic low threshold detin pin ac coupled 200 300 400 mv a th-h amplitude diagnostic high threshold detin pin ac coupled 900 1100 1200 mv f th-l frequency diagnostic low thresholds detin pin ac coupled 13 16.5 20 khz f th-h frequency diagnostic high thresholds detin pin ac coupled 24 29.5 38 khz
typical performance characteristics lnbh23 22/32 doc id 13356 rev 8 9 typical performance characteristics (refer to the typical application circuit, t j from 0 to 85 c, en = 1, vsel=llc=ten=pcl=itest=ttx=aux=0, r sel = 11 k , dsqin=low, v i = 12 v, i o = 50 ma, unless otherwise stated. typical values are referred to t j = 25 c. v o =v orx pin voltage. see software description section for i2c access to the system register). figure 8. output voltage vs. temperature figure 9. output voltage vs. temperature figure 10. output voltage vs. temperature figure 11. output voltage vs. temperature figure 12. load regulation vs. temperature figure 13. supply current vs. temperature v cc =12v, i o =50ma, v o =13v range en=1, vsel=llc=0 12.6 12.8 13 13.2 13.4 13.6 13.8 14 -10 0 10 20 30 40 50 60 70 80 90 t [c] v o [v] v cc =12v, i o =50ma, v o =13v range en=1, vsel=llc=0 12.6 12.8 13 13.2 13.4 13.6 13.8 14 -10 0 10 20 30 40 50 60 70 80 90 t [c] v o [v] v cc =12v, i o =50ma, v o =14v range en=llc=1, vsel=0 13.6 13.8 14 14.2 14.4 14.6 14.8 15 -10 0 10 20 30 40 50 60 70 80 90 t [c] v o [v] v cc =12v, i o =50ma, v o =14v range en=llc=1, vsel=0 13.6 13.8 14 14.2 14.4 14.6 14.8 15 -10 0 10 20 30 40 50 60 70 80 90 t [c] v o [v] en=vsel=1, llc=0 v cc =12v, i o =50ma, v o =18v range 17.8 18 18.2 18.4 18.6 18.8 19 19.2 -10 0 10 20 30 40 50 60 70 80 90 t [c] v o [v] en=vsel=1, llc=0 v cc =12v, i o =50ma, v o =18v range 17.8 18 18.2 18.4 18.6 18.8 19 19.2 -10 0 10 20 30 40 50 60 70 80 90 t [c] v o [v] en=vsel=llc=1 v cc =12v, i o =50ma, v o =19.5v range 18.5 18.7 18.9 19.1 19.3 19.5 19.7 19.9 20.1 20.3 -10 0 10 20 30 40 50 60 70 80 90 t [c] v o [v] en=vsel=llc=1 v cc =12v, i o =50ma, v o =19.5v range 18.5 18.7 18.9 19.1 19.3 19.5 19.7 19.9 20.1 20.3 -10 0 10 20 30 40 50 60 70 80 90 t [c] v o [v] v cc =12v i o =from 50 to 750ma -160 -140 -120 -100 -80 -60 -40 -20 0 -10 0 10 20 30 40 50 60 70 80 90 t [c] load [mv] v cc =12v i o =from 50 to 750ma -160 -140 -120 -100 -80 -60 -40 -20 0 -10 0 10 20 30 40 50 60 70 80 90 t [c] load [mv] en=llc=vsel=1, ten=ttx=0 v cc =12v, i o =no load 0 2 4 6 8 10 12 14 16 -10 0 10 20 30 40 50 60 70 80 90 t [c] i in [ma] en=llc=vsel=1, ten=ttx=0 v cc =12v, i o =no load 0 2 4 6 8 10 12 14 16 -10 0 10 20 30 40 50 60 70 80 90 t [c] i in [ma]
lnbh23 typical performance characteristics doc id 13356 rev 8 23/32 figure 14. supply current vs. temperature figure 15. dynamic overload protection on time vs. temperature figure 16. dynamic overload protection off time vs. temperature figure 17. output current limiting vs. r sel figure 18. output current limiting vs. temperature figure 19. output current limiting vs. temperature en=ten=ttx=llc=vsel=1 v cc =12v i o =no load 0 5 10 15 20 25 30 35 40 -10 0 10 20 30 40 50 60 70 80 90 t [c] i i [ma] en=ten=ttx=llc=vsel=1 v cc =12v i o =no load 0 5 10 15 20 25 30 35 40 -10 0 10 20 30 40 50 60 70 80 90 t [c] i i [ma] v cc =12v, v o =shorted to gnd 40 50 60 70 80 90 100 110 120 130 140 -10 0 10 20 30 40 50 60 70 80 90 t [c] t on [ms] v cc =12v, v o =shorted to gnd 40 50 60 70 80 90 100 110 120 130 140 -10 0 10 20 30 40 50 60 70 80 90 t [c] t on [ms] v cc =12v v o =shorted to gnd 600 700 800 900 1000 1100 1200 -10 0 10 20 30 40 50 60 70 80 90 t [c] t off [ms] v cc =12v v o =shorted to gnd 600 700 800 900 1000 1100 1200 -10 0 10 20 30 40 50 60 70 80 90 t [c] t off [ms] v cc =12v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 10 12 14 16 18 20 22 24 26 28 30 32 r sel [k ] i max [ma] v cc =12v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 10 12 14 16 18 20 22 24 26 28 30 32 r sel [k ] i max [ma] v cc =12v, r sel =11k 750 800 850 900 950 1000 -10 0 10 20 30 40 50 60 70 80 90 t [c] i max [ma] v cc =12v, r sel =11k 750 800 850 900 950 1000 -10 0 10 20 30 40 50 60 70 80 90 t [c] i max [ma] v cc =12v, r sel =22k 300 350 400 450 500 550 -10 0 10 20 30 40 50 60 70 80 90 t [c] i max [ma] v cc =12v, r sel =22k 300 350 400 450 500 550 -10 0 10 20 30 40 50 60 70 80 90 t [c] i max [ma]
typical performance characteristics lnbh23 24/32 doc id 13356 rev 8 figure 20. tone frequency vs. temperature figure 21. tone amplitude vs. temperature figure 22. tone duty cycle vs. temperature figure 23. tone rise time vs. temperature figure 24. tone fall time vs. temperature figure 25. output backward current vs. temperature v cc =12v, i o =50ma en=ten=ttx=1 18 19 20 21 22 23 24 25 26 -10 0 10 20 30 40 50 60 70 80 90 t [c] f tone [khz] v cc =12v, i o =50ma en=ten=ttx=1 18 19 20 21 22 23 24 25 26 -10 0 10 20 30 40 50 60 70 80 90 t [c] f tone [khz] en=ten=ttx=1 v cc =12v, i o =50ma 400 500 600 700 800 900 1000 -10 0 10 20 30 40 50 60 70 80 90 t [c] a tone [mv] en=ten=ttx=1 v cc =12v, i o =50ma 400 500 600 700 800 900 1000 -10 0 10 20 30 40 50 60 70 80 90 t [c] a tone [mv] v cc =12v, i o =50ma en=ten=ttx=1 45 46 47 48 49 50 51 52 53 54 55 -10 0 10 20 30 40 50 60 70 80 90 t [c] d tone [%] v cc =12v, i o =50ma en=ten=ttx=1 45 46 47 48 49 50 51 52 53 54 55 -10 0 10 20 30 40 50 60 70 80 90 t [c] d tone [%] v cc =12v, i o =50ma en=ten=ttx=1 4 5 6 7 8 9 10 11 12 13 14 -10 0 10 20 30 40 50 60 70 80 90 t [c] t r [s] v cc =12v, i o =50ma en=ten=ttx=1 4 5 6 7 8 9 10 11 12 13 14 -10 0 10 20 30 40 50 60 70 80 90 t [c] t r [s] v cc =12v, i o =50ma en=ten=ttx=1 4 5 6 7 8 9 10 11 12 13 14 -10 0 10 20 30 40 50 60 70 80 90 t [c] t f [s] v cc =12v, i o =50ma en=ten=ttx=1 4 5 6 7 8 9 10 11 12 13 14 -10 0 10 20 30 40 50 60 70 80 90 t [c] t f [s] v cc =12v, v obk =21v externally forced en=0 -4 -3 -2 -1 0 -10 0 10 20 30 40 50 60 70 80 90 t [c] i obk [ma] v cc =12v, v obk =21v externally forced en=0 -4 -3 -2 -1 0 -10 0 10 20 30 40 50 60 70 80 90 t [c] i obk [ma]
lnbh23 typical performance characteristics doc id 13356 rev 8 25/32 figure 26. dc-dc converter efficiency vs. temperature figure 27. 22 khz tone waveform figure 28. dsqin tone enable transient response figure 29. dsqin tone disable transient response en=vsel=llc=1 v cc =12v, i o =750ma 40 50 60 70 80 90 100 -10 0 10 20 30 40 50 60 70 80 90 t [c] eff [%] en=vsel=llc=1 v cc =12v, i o =750ma 40 50 60 70 80 90 100 -10 0 10 20 30 40 50 60 70 80 90 t [c] eff [%] v cc =12v en=ten=ttx=1 lnb out dsqin v cc =12v en=ttx=1, ten=0 lnb out dsqin v cc =12v en=ttx=1, ten=0 lnb out
package mechanical data lnbh23 26/32 doc id 13356 rev 8 10 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
lnbh23 package mechanical data doc id 13356 rev 8 27/32 table 14. qfn32 (5 x 5 mm.) mechanical data dim. (mm.) min. typ. max. a 0.80 0.90 1.00 a1 0 0.02 0.05 a3 0.20 b 0.18 0.25 0.30 d 4.85 5.00 5.15 d2 3.20 3.70 e 4.85 5.00 5.15 e2 3.20 3.70 e0.50 l 0.30 0.40 0.50 ddd 0.08 figure 30. qfn32 package dimensions 7376875/e
package mechanical data lnbh23 28/32 doc id 13356 rev 8 dim. mm. inch. min. typ. max. min. typ. max. a 2.15 2.47 0.0 8 5 0.0 9 7 a2 2.15 2.40 0.0 8 5 0.0 9 4 a 1 0 0.075 0 0.00 3 b 0. 33 0.51 0.01 3 0.020 c0.2 3 0. 3 2 0.00 9 0.01 3 d (1) 10.10 10.50 0. 398 0.41 3 e (1) 7.4 7.6 0.2 9 1 0.2 99 e0. 8 0.0 3 1 e 38 . 8 0. 3 46 g 0.10 0.004 g1 0.06 0.002 h 10.10 10.50 0. 398 0.41 3 h 0.40 0.016 l 0.55 0. 8 5 0.022 0.0 33 n 10 (m a x) x 4.10 4.70 0.161 0.1 8 5 y4. 9 0 5.50 0.1 93 0.217 power ss o-24 mechanical data 7412 8 1 8 _a (1) ?d a nd e ? do not incl u de mold fl as h or prot us ion s - mold fl as h or prot us ion s s h a ll not exceed 0.15 mm. (0.006 ? )
lnbh23 package mechanical data doc id 13356 rev 8 29/32 dim. mm. inch. min. typ. max. min. typ. max. a 33 0 12. 99 2 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n60 2. 3 62 t 3 0.4 1.1 9 7 ao 10. 8 11.0 0.425 0.4 33 bo 10.7 10. 9 0.421 0.42 9 ko 2.65 2. 8 5 0.104 0.112 po 3 . 9 4.1 0.154 0.161 p 1 11. 9 12.1 0.46 9 0.476 w2 3 .7 24. 3 0. 933 0. 9 57 tape & reel power ss o-24 mechanical data
package mechanical data lnbh23 30/32 doc id 13356 rev 8 dim. mm. inch. min. typ. max. min. typ. max. a 33 0 12. 99 2 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n 99 101 3 . 898 3 . 9 76 t 14.4 0.567 ao 5.25 0.207 bo 5.25 0.207 ko 1.1 0.04 3 po 4 0.157 p 8 0. 3 15 tape & reel qfnxx/dfnxx (5x5 mm.) mechanical data
lnbh23 revision history doc id 13356 rev 8 31/32 11 revision history table 15. document revision history date revision changes 02-apr-2007 1 initial release. 15-nov-2007 2 added note 2 on ta bl e 3 . 11-jan-2008 3 added: new package qfn32 and ta bl e 5 . 26-mar-2008 4 modified: mechanical data for qfn32 figure 30 on page 27 and table 14 on page 27 . 08-jan-2009 5 modified: esd parameter table 3 on page 11 . 23-mar-2009 6 modified: y dimension mechanical data for powersso-24 on page 28 . 29-nov-2010 7 modified: table 10 on page 20 . 01-feb-2013 8 modified: maximum clock frequency max. value table 9 on page 20 .
lnbh23 32/32 doc id 13356 rev 8 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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